Wednesday 18 April 2012

User’s View of a Program


Segmentation


  • Memory-management scheme that supports user view of memory.
  • A program is a collection of segments.  A segment is a logical unit such as:
                    main program,
                    procedure,
                    function,
                    method,
                    object,
                    local variables, global variables,
                    common block,
                    stack,
                    symbol table, arrays

Shared Pages


  • Shared code
  1. One copy of read-only (reentrant) code shared among processes (i.e., text editors, compilers, window systems).
  2. Shared code must appear in same location in the logical address space of all processes.
  • Private code and data
  1. Each process keeps a separate copy of the code and data.
  2. The pages for the private code and data can appear anywhere in the logical address space.

Inverted Page Table


  • One entry for each real page of memory.
  • Entry consists of the virtual address of the page stored in that real memory location, with information about the process that owns that page.
  • Decreases memory needed to store each page table, but increases time needed to search the table when a page reference occurs.
  • Use hash table to limit the search to one — or at most a few — page-table entries.

Hashed Page Tables


  • Common in address spaces > 32 bits.
  • The virtual page number is hashed into a page table. This page table contains a chain of elements hashing to the same location.
  • Virtual page numbers are compared in this chain searching for a match. If a match is found, the corresponding physical frame is extracted.

Address-Translation Scheme


  • Address-translation scheme for a two-level 32-bit paging architecture



Two-Level Page-Table Scheme


Two-Level Paging Example


  • A logical address (on 32-bit machine with 4K page size) is divided into:
  1. a page number consisting of 20 bits.
  2. a page offset consisting of 12 bits.
  • Since the page table is paged, the page number is further divided into:
  1. a 10-bit page number.
  2. a 10-bit page offset.

Hierarchical Page Tables


  • Break up the logical address space into multiple page tables.
  • A simple technique is a two-level page table.

Page Table Structure


  • Hierarchical Paging
  • Hashed Page Tables
  • Inverted Page Tables

Valid (v) or Invalid (i) Bit In A Page Table


Memory Protection


  • Memory protection implemented by associating protection bit with each frame.
  • Valid-invalid bit attached to each entry in the page table:
  1. “valid” indicates that the associated page is in the process’ logical address space, and is thus a legal page.
  2. “invalid” indicates that the page is not in the process’ logical address space.

Effective Access Time


  • Associative Lookup = e time unit
  • Assume memory cycle time is 1 microsecond
  • Hit ratio – percentage of times that a page number is found in the associative registers; ration related to number of associative registers.
  • Hit ratio = a
  • Effective Access Time (EAT)
                        EAT = (1 + e) a + (2 + e)(1 – a)
                               = 2 + ea

Paging Hardware With TLB


Associative Memory


  • Associative memory – parallel search
  • Address translation (A´, A´´)
  1. If A´ is in associative register, get frame # out.
  2. Otherwise get frame # from page table in memory

Implementation of Page Table


  • Page table is kept in main memory.
  • Page-table base register (PTBR) points to the page table.
  • Page-table length register (PRLR) indicates size of the page table.
  • In this scheme every data/instruction access requires two memory accesses.  One for the page table and one for the data/instruction.
  • The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs)

Monday 9 April 2012

Free Frames


Paging Example


Paging Example


Address Translation Architecture


Address Translation Scheme


  • Address generated by CPU is divided into:
  1. Page number (p) – used as an index into a page table which contains base address of each page in physical memory.
  2. Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit.

Paging


  • Logical address space of a process can be noncontiguous; process is allocated physical memory whenever the latter is available.
  • Divide physical memory into fixed-sized blocks called frames (size is power of 2, between 512 bytes and 8192 bytes).
  • Divide logical memory into blocks of same size called pages.
  • Keep track of all free frames.
  • To run a program of size n pages, need to find n free frames and load program.
  • Set up a page table to translate logical to physical addresses.
  • Internal fragmentation.

Fragmentation


  • External Fragmentation – total memory space exists to satisfy a request, but it is not contiguous.
  • Internal Fragmentation – allocated memory may be slightly larger than requested memory; this size difference is memory internal to a partition, but not being used.
  • Reduce external fragmentation by compaction
  1. Shuffle memory contents to place all free memory together in one large block.
  2. Compaction is possible only if relocation is dynamic, and is done at execution time.
  3. I/O problem
*Latch job in memory while it is involved in I/O.
*Do I/O only into OS buffers.

Dynamic Storage-Allocation Problem


How to satisfy a request of size n from a list of free holes.
  • First-fit:  Allocate the first hole that is big enough.
  • Best-fit:  Allocate the smallest hole that is big enough; must search entire list, unless ordered by size.  Produces the smallest leftover hole.
  • Worst-fit:  Allocate the largest hole; must also search entire list.  Produces the largest leftover hole.
First-fit and best-fit better than worst-fit in terms of speed and storage utilization.

Hardware Support for Relocation and Limit Registers


Schematic View of Swapping


Swapping


  • A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution.
  • Backing store – fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images.
  • Roll out, roll in – swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executed.
  • Major part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped.
  • Modified versions of swapping are found on many systems, i.e., UNIX, Linux, and Windows.

Overlays for a Two-Pass Assembler


Overlays


  • Keep in memory only those instructions and data that are needed at any given time.
  • Needed when process is larger than amount of memory allocated to it.
  • Implemented by user, no special support needed from operating system, programming design of overlay structure is complex

Dynamic Linking


  • Linking postponed until execution time.
  • Small piece of code, stub, used to locate the appropriate memory-resident library routine.
  • Stub replaces itself with the address of the routine, and executes the routine.
  • Operating system needed to check if routine is in processes’ memory address.
  • Dynamic linking is particularly useful for libraries.

Dynamic Loading


  • Routine is not loaded until it is called
  • Better memory-space utilization; unused routine is never loaded.
  • Useful when large amounts of code are needed to handle infrequently occurring cases.
  • No special support from the operating system is required implemented through program design.

Dynamic relocation using a relocation register


Memory Management Unit (MMU)


  • Hardware device that maps virtual to physical address.
  • In MMU scheme, the value in the relocation register is added to every address generated by a user process at the time it is sent to memory.
  • The user program deals with logical addresses; it never sees the real physical addresses.

Logical vs. Physical Address Space


  • The concept of a logical address space that is bound to a separate physical address space is central to proper memory management.
  1. Logical address – generated by the CPU; also referred to as virtual address.
  2. Physical address – address seen by the memory unit.
  • Logical and physical addresses are the same in compile-time and load-time address-binding schemes; logical (virtual) and physical addresses differ in execution-time address-binding scheme.

Multistep Processing of a User Program


Binding of Instructions and Data to Memory


Address binding of instructions and data to memory addresses can
happen at three different stages.
  • Compile time:  If memory location known a priori, absolute code can be generated; must recompile code if starting location changes.
  • Load time:  Must generate relocatable code if memory location is not known at compile time.
  • Execution time:  Binding delayed until run time if the process can be moved during its execution from one memory segment to another.  Need hardware support for address maps (e.g., base and limit registers). 

Traffic Deadlock


Combined Approach to Deadlock Handling


  • Combine the three basic approaches
  1. prevention
  2. avoidance
  3. detection
     allowing the use of the optimal approach for each of resources in the system.
  • Partition resources into hierarchically ordered classes.
  • Use most appropriate technique for handling deadlocks within each class.

Recovery from Deadlock: Resource Preemption


  • Selecting a victim – minimize cost.
  • Rollback – return to some safe state, restart process for that state.
  • Starvation –  same process may always be picked as victim, include number of rollback in cost factor.

Recovery from Deadlock : Process Termination


  • Abort all deadlocked processes.
  • Abort one process at a time until the deadlock cycle is eliminated.
  • In which order should we choose to abort?
  1. Priority of the process.
  2. How long process has computed, and how much longer to completion.
  3. Resources the process has used.
  4. Resources process needs to complete.
  5. How many processes will need to be terminated.
  6. Is process interactive or batch?